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Advantages of Gemini Compute-in-Memory in Power and Performance Applications Published January 2026 Author: Mark Wright Introduction In the paper on compute-in-memory (CIM) devices, we compared compute-in-memory with other architectures and showed that compute-in-memory (CIM) can significantly reduce power consumption and improve performance in many applications. This article reviews GSI's CIM Gemini® associative processing technology and shows how it can be applied to a wide range of application scenarios. Overview of Compute-in-Memory (CIM) GSI's CIM Gemini® associative processing technology is based on in-memory computing (IMC) and is implemented in Gemini-I® and Gemini-II® devices. The technology is based on the Tanimoto distance metric and is designed for AI inference and other applications requiring high throughput and low power consumption. CIM differs from traditional von Neumann architecture in that computation is performed in or near memory, thereby reducing data movement. This is particularly important for data-centric applications (such as AI/ML), where data movement costs can dominate total system power consumption and latency. Figure 1 is a side-by-side conceptual illustration of three architecture types: Figure 1: Comparison of computing architecture types—von Neumann, near-memory computing, and compute-in-memory GSI Technology Associative Processing Unit (APU) CIM Architecture Figure 2: APU CIM architecture overview—Gemini-I chip photo and associative memory and compute logic Figure 2 is an actual wafer photo of the GSI APU Gemini-I chip. The design builds on GSI's 28 years of experience in DRAM/SRAM. Unlike CPUs/GPUs, the architecture has no discrete blocks that need to move data back and forth within the chip. APU bit processors are groups of dedicated SRAM bits that can read bitlines simultaneously, thereby performing Boolean operations during the read process. The first-generation Gemini-I has 2 million bit engines and can perform more than 20 quadrillion operations per second at 500 MHz. In-memory computing eliminates the memory transfer bottleneck that limits traditional architectures. The architecture departs from the traditional von Neumann model of separate computing and storage. In this CIM architecture, computing and storage are performed in place within the bit processor array. APU Applications The advantages of compute-in-memory span AI/ML, vector search, real-time analytics, image classification, and high-performance computing (HPC) applications, including synthetic aperture radar (SAR), genomics, and cryptography. Gemini-I has been used in Biovia Pipeline Pilot for drug retrieval through distance metrics based on Tanimoto.[1] GSI's Fast Vector Search (FVS) library and API support traditional vector search and SHA processing for password recovery. Gemini-I has been used for high-performance computing such as synthetic aperture radar image generation on a 1U mobile server. Northern Arizona University has published research on cryptographic processing based on this architecture.[2] Cornell University has published circuit-level research on bit matching in DNA read alignment.[3] These examples show that APU technology has industrial application value in real-time processing and performance/watt/cost efficiency. GSI APU-CIM Architecture Advantages and Business Value GSI's APU represents a paradigm shift, providing associative, massively parallel, true compute-in-memory capabilities. High energy efficiency and low power consumption: The architecture performs computation in memory and can implement Boolean operations in a single clock cycle. Compared with traditional von Neumann GPUs, the APU architecture only needs to transfer data over a distance of about 20 microns. This extremely fast processing array can also be loaded from register storage. Because this storage capacity is large—larger than the in-place compute storage—and distributed, at about 100 microns from the processing storage, we again see data movement reduced by about two to three orders of magnitude, thereby accelerating processing and significantly reducing power consumption. Such data transfers on the first-generation APU are about 0.05 picojoules per bit. Figure 3: Traditional von Neumann GPU core structure; Figure 4: APU CIM bit processor with large working storage support Flexibility The APU architecture does not impose a predefined framework on programmers. Instead, any framework—including custom bit widths down to a single bit—can be used natively in the device. With this approach, many different bit widths can be designed, and even cycle-by-cycle dynamic precision can be achieved, saving compute and storage resources without affecting accuracy. This leaves room for future algorithms and can support bit widths not yet conceived. One example of native support for new architectures is the ability to support micro-scaling formats (MX Format). The architecture can now also handle binary neural network (BNN) frameworks. Sustainable application performance The combination of millions of bit processors in the APU array and large, tightly coupled distributed storage means that, for models that fit into the array, the architecture can eliminate application memory bottlenecks. This delivers 100% core utilization, maximum throughput, and minimum power consumption. The second-generation Gemini-II integrates 96MB of register storage, enabling a single device to process larger models at the edge or to build data center systems that can process very large models at full core utilization. Scalability Because compute-in-memory devices are, in a sense, memory, systems using these components can scale in the same way as expanding system memory—simply by adding more components, without complex interconnects. With this approach, it is common for a single low-cost server system to be equipped with 8 or 16 cards. Large-scale expansion can be achieved with commercial 10gE server interconnects. These advantages combine to enable users to deploy systems from edge to data center with optimal TCO (performance/watt/dollar). Source: GSI Technology, Inc. Comparison High-performance computing example: synthetic aperture radar processing Features: variable "random" variable precision, parallel processing, one-to-many sensor data input to the processor Five-year power cost comparison for SAR processing: Intel CPU, Nvidia V100, and GSI APU Gemini-I Custom search application: small-molecule drug discovery Features: desired low-threshold comparison, long vector length: tested up to 8000-bit width Biovia Pipeline Pilot customer benchmark: Intel CPU vs. GSI APU Gemini-I High-performance computing: salted response-based cryptography comparison (SHA-1) Features: cryptographic processing SHA-1 cryptography comparison: AMD EPYC, Nvidia A100, and GSI APU Gemini-I HNSW index construction acceleration Features: parallelism and hardware graph construction acceleration Deep1B subset index construction time: Pgvector, Hnswlib, and GXL Conclusion GSI's in-memory computing represents a major shift in the computing paradigm, and its proven SRAM technology is ready for large-scale deployment. As the costs of traditional computing and memory in energy, cooling, and diminishing returns to scale continue to rise, in-memory computing has been proven to handle traditional von Neumann processing workloads more efficiently and is increasingly becoming a key component of modern IT infrastructure, making previously economically infeasible applications and operations possible. We have described the differentiated performance this technology demonstrates across several application types—sometimes orders of magnitude better than traditional computing. This technology is particularly important for three types of processing: inference workloads that can be accelerated by softmax can be natively handled with Tanimoto classification; high-performance computing based on or efficiently convertible to binary representation processing; and processing that can be classified as highly repetitive loops, especially when one or two of the aforementioned differentiating characteristics are present. Source: GSI Technology, Inc. For more information, please contact info@upmic.io [1] https://gsitechnology.com/wp-content/uploads/sites/default/files/files/GSIT-Weizmann-Case-Study.pdf [2] https://jan.ucc.nau.edu/mg2745/publications/Lee_DUAC_ICPPW2023.pdf [3] https://gsitechnology.com/wp-content/uploads/sites/default/files/files/Accelerating-Seed-Location-Filtering-in-DNA-Read-Mapping-Using-Commercial-Compute-in-SRAM-Architecture.pdf